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Si9137
Vishay Siliconix
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications
FEATURES
D D D D D D D D D D D D Up to 95% Efficiency "3% Total Regulation (Line, Load and Temperature) 5.5-V to 30-V Input Voltage Range 3.3-V, 5-V, and Adjustable 5- to 12-V Outputs 300-kHz Low-Noise Fixed Frequency Operation Precision 3.3-V Reference Output 5-V/30-mA Linear Regulator Output High Efficiency Pulse Skipping Mode Operation at Light Load Programmable Output Sequencing Only Three Inductors RequiredNo Transformer LITTLE FOOTR Optimized Output Drivers Internal Soft-Start D D D D D
Minimal External Control Components 28-Pin SSOP Package Output Overvoltage Protection Output Undervoltage Shutdown Power-Good Output (RESET)
APPLICATIONS
D D D D D D Notebook and Subnotebook Computers PDAs and Mobile Communicators Portable Display Multimedia Set-Top Box Telecommunications Infrastructure Distributed Power Conversion
DESCRIPTION
The Si9137 is a current-mode PWM and PSM converter controller, with two synchronous buck converters (3.3 V and 5 V) and an adjustable flyback (non-isolated buck-boost) converter whose output can be set between 5 and 12 V with an external resistor divider. Designed for portable devices, it offers a total of five power outputs (three tightly regulated dc/dc converter outputs, a precision 3.3-V reference and a 5-V LDO output) and includes on-board pre-programmed power-up sequencing, power-good signal with delay, internal frequency compensation networks and automatic boot-strapping. It requires minimum external components and is capable of achieving conversion efficiencies approaching 95%.
The Si9137 is available in a 28-pin SSOP package and specified to operate over the extended commercial (0_C to 90_C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
VIN (5.5 V to 30 V)
VL (5.0 V)
5-V Linear Regulator
3.3-V Voltage Reference
VREF (+3.3 V)
+3.3 V/6 A
3.3-V SMPS
5-V SMPS
+5 V/6 A
5- to 12-V SMPS Programmable
VFLYBACK +5- to +12-V/500 mA Adjustable
SEQ RUN/STOP
Power-Up Sequence
Power_Good
RESET (Power_Good)
Document Number: 70874 S-20642--Rev. B, 13-May-02
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Si9137
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +36 V PGND to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.5 V BST3, BST5, BSTFY to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +36 V VL Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous LX3 to BST3; LX5 to BST5; LXFY to BSTFY . . . . . . . . . . . . . . -6.5 V to 0.3 V Inputs/Outputs to GND (CS3, CS5, CSP, CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (VL +0.3 V) RUN/STOP, SEQ, RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V DL3, DL5, DLFY to PGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (VL +0.3 V) DH3 to LX3, DH5 to LX5, DHFY to LXFY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (BSTx +0.3 V) Continuous Power Dissipation (TA = 70_C)a 28-Pin SSOPb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 mW Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40_C to 125_C Lead Temperature (Soldering, 10 Sec.) . . . . . . . . . . . . . . . . . . . . . . . . . 300_C Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 9.52 mW/_C above 70_C.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SPECIFICATIONS
Test Conditions Parameter 3.3-V Buck Controller
Total Regulation (Line, Load, and Temperature) Line Regulation Load Regulation Current Limit Bandwidth Phase Margin VIN = 6 to 30 V, 0 < VCS3 - VFB3 < 90 mV VIN = 6 to 30 V 0 < VCS3 - VFB3 < 90 mV VCS3 - VFB3 L = 10 mH, C = 330 mF RSENSE = 20 mW 90 125 50 65 3.22 3.32 3.42 "0.5 "0.5 160 V % mV kHz _ VIN = 15 V , IVL = IREF = 0 mA TA = 0_C to 90_C, All Controllers ON
Limits Mina Typb Maxa Unit
5-V Buck Controller
Total Regulation (Line, Load, and Temperature) Line Regulation Load Regulation Current Limit Bandwidth Phase Margin VIN = 6 to 30 V, 0 < VCS5 - VFB5 < 90 mV VIN = 6 to 30 V 0 < VCS5 - VFB5 < 90 mV VCS5 - VFB5 L = 10 mH, C = 330 mF RSENSE = 20 mW 90 125 50 65 4.87 5.02 5.17 0.5 0.5 160 V % mV kHz _
5- to 12-V Flyback Controller
Total Regulation (Line, Load, and Temperature) Output Voltage Set to 12 V Line Regulation Load Regulation Current Limit Bandwidth Phase Margin VIN = 6 to 30 V, 0 < VCSP - VCSN < 300 mV R5 = 26.4 kW, R6 = 10 kW (See Figure 1) VIN = 6 to 30 V 0 < VCSP - VFBN < 300 mV VCSP - VCSN L = 10 mH, C = 100 mF RSENSE = 100 mW, Ccomp = 120 pF 330 410 10 65 11.4 12.0 12.6 0.5 0.5 500 V % mV kHz _
Internal Regulator
VL Output VL Fault Lockout Voltage VL Fault Lockout Hysteresis VL /FB5 Switchover Voltage VL /FB5 Switchover Hysteresis www.vishay.com FB5 Rising Edge 4.2 75 All Controllers OFF, VIN >5.5 V, 0 2
Si9137
Vishay Siliconix
SPECIFICATIONS
Test Conditions Parameter Reference
REF Output REF Load Regulation No External Load 0 to 1 mA 3.24 3.30 30 3.36 75 V mV VIN = 15 V , IVL = IREF = 0 mA TA = 0_C to 90_C, All Controllers ON
Limits Mina Typb Maxa Unit
Supply Current
Supply Current*Shutdown Supply Current*Operation RUN/STOP = GND, All Converters OFF, No Load All Controllers ON, No Load, fOSC = 300 kHz 25 1100 60 1800 mA m
Oscillator
Oscillator Frequency Maximum Duty Cycle 270 92 300 95 330 kHz %
Fault Detection 3.3-V and 5-V Outputs
Overvoltage Trip Threshold Overvoltage-Fault Propagation Delay Output Undervoltage Threshold Output Undervoltage Lockout Time With Respect To Unloaded Output Voltage CS3 or CS5 Driven 2% Above Overvoltage Trip Threshold With Respect to Unloaded Output Voltage From each SMPS Enabled -40 16 6 10 1.5 -30 20 -20 24 14 % ms % ms
RESET
RESET Start Threshold RESET Propagation Delay (Falling) RESET Delay Time (Rising) With Respect To Unloaded Output Voltage Rising Edge Falling Edge, FB3 or FB5 Driven 2% Above Overvoltage or 2% Below Undervoltage Lockout Thresholds With Respect to 2nd SMPS Lockout Time Done 92 -5.5 1.5 107 122 % ms ms
Inputs and Outputs
Feedback Input Leakage Current Input Leakage Current Gate Driver Sink/Source Current (Buck) Gate Driver On-Resistance (Buck) Gate Driver Sink/Source Current (Flyback) Gate Driver On-Resistance (Flyback) RESET Output Low Voltage RESET High Voltage Leakage FBFY = 3.3 V RUN/STOP, SEQ, VIN = 0 V or VL DL3, DH3, DL5, DH5 Forced to 2 V High or Low DHFY, DLFY Forced to 2 V High or Low RESET, ISINK = 4 mA RESET = 5 V 1 2 0.2 15 0.4 1 7 1 "1 mA m A W A W V mA
RUN/STOP
VIL VIH 2.4 0.8 V
Notes a. The algebraic convention is used whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing, and are measured at TA = 25_C.
Document Number: 70874 S-20642--Rev. B, 13-May-02
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Si9137
Vishay Siliconix
PIN CONFIGURATION
RESET FBFY BSTFY DHFY LXFY DLFY CSP CSN COMP GND REF RUN/STOP SEQ CS5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP-28 Top View 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CS3 FB3 DH3 LX3 BST3 DL3 VIN VL FB5 PGND DL5 BST5 LX5 DH5
ORDERING INFORMATION
Part Number
SI9137LG
Temperature Range
0 to 90_C
VOUT
3.3 V, 5 V, 5 to ADJ V
Evaluation Board
Si9137DB
Temperature Range
0 to 90_C
Board Type
Surface Mount
PIN DESCRIPTION
Pin
1 2 3 4 5 6 7 8 9 10 11 12
Symbol
RESET FBFY BSTFY DHFY LXFY DLFY CSP CSN COMP GND REF RUN/STOP
Description
Open drain NMOS output active-low timed reset output. RESET swings GND to VL. Goes high after a fixed 32,000 clock cycle delay following proper power-up of all supply outputs indicating Power_Good. Feedback for flyback converter. Normally connected to an external resistor divider used to set the flyback output voltage. Boost capacitor connection for flyback converter. Gate-drive output for flyback high-side MOSFET. Inductor connection for flyback converter. Gate-drive output for flyback low-side MOSFET. Current sense positive input for flyback converter. Current sense negative input for flyback converter. Flyback compensation connection, if required. Analog ground. 3.3-V internal reference. Triple controller ON/OFF control. Logic threshold is 0.8 to 2.4 V. When RUN/STOP is low, all converters are off and supply current is 25-mA typical, 60-mA maximum. Pin Strap input that selects SMPS power-up sequence (pin should be fixed to GND, REF or VL): SEQ = GND: 5-V then 3.3-V then adjustable 5- to 12-V output SEQ = VL: 3.3-V then 5-V then adjustable 5- to 12-V output SEQ = REF: 3.3-V then 5-V then adjustable 5- to 12-V output, high impedance error detect mode. Current sense input for 5-V buck controller. Gate-drive output for 5-V buck high-side MOSFET. Inductor connection for buck 5-V. Boost capacitor connection for 5-V buck converter. Gate-drive output for 5-V buck low-side MOSFET. Power ground. Feedback for 5-V buck. 5-V logic supply voltage for internal circuitry. Input voltage Gate-drive output for 3.3-V buck low-side MOSFET. Boost capacitor connection for 3.3-V buck converter. Inductor connection for 3.3-V buck low-side MOSFET. Gate-drive output for 3.3-V buck high-side MOSFET. Feedback for 3.3-V buck. Current sense input for 3.3-V buck. Document Number: 70874 S-20642--Rev. B, 13-May-02
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SEQ
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 www.vishay.com
CS5 DH5 LX5 BST5 DL5 PGND FB5 VL VIN DL3 BST3 LX3 DH3 FB3 CS3
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Si9137
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Efficiency vs. 3.3-V Output Current
100 Frequency = 300 kHz 90 VIN = 6 V Efficiency (%) 80 30 V 70 5 V, 12 V No Load 60 60 15 V Efficiency (%) 80 30 V 90 VIN = 6 V 15 V 100 Frequency = 300 kHz
Efficiency vs. 5.0-V Output Current
70 3.3 V, 12 V No Load
50 0.001 0.01 0.1 Current (A) 1 10
50 0.001 0.01 0.1 Current (A) 1 10
Efficiency vs. 5- to 12-V Adjustable Output Current (Output Set to 12 V)
85 Frequency = 300 kHz 80 6V 75 Efficiency (%) 30 V VIN = 15 V
70
65 5 V, 3.3 V No Load 60
55 0.001 0.01 Current (A) 0.1 1
Document Number: 70874 S-20642--Rev. B, 13-May-02
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Si9137
Vishay Siliconix
TYPICAL WAVEFORMS
PWM Loading 5-V Converter
(VIN = 10 V)
PWM Unloading 5-V Converter
(VIN = 10 V)
VOUT (100 mV/div)
VOUT (100 mV/div)
Load (1 A/div)
Load (1 A/div)
20.0 ms/div
20.0 ms/div
PSM to PWM 5-V Converter
(VIN = 10 V) VOUT (100 mV/div)
PWM to PSM 5-V Converter
(VIN = 10 V) VOUT (100 mV/div)
Load (1 A/div)
Load (1 A/div)
100 ms/div
100 ms/div
PSM Operation 5-V Converter
(VIN = 10 V) VOUT (100 mV/div)
PWM Operation 5-V Converter
(VIN = 10 V) VOUT (100 mV/div)
Inductor Node (L X5)
Inductor Node (L X5)
Inductor Current (1A/div)
Inductor Current (1A/div)
10.0 ms/div
2.00 ms/div
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Document Number: 70874 S-20642--Rev. B, 13-May-02
Si9137
Vishay Siliconix
TYPICAL WAVEFORMS
PWM Loading 3-V Converter
(VIN = 10 V)
PWM Unloading 3-V Converter
(VIN = 10 V)
VOUT (100 mV/div)
VOUT (100 mV/div)
Load (1 A/div)
Load (1 A/div)
20.0 ms/div
20.0 ms/div
PSM to PWM 3-V Converter
(VIN = 10 V) VOUT (100 mV/div)
PWM to PSM 3-V Converter
(VIN = 10 V) VOUT (100 mV/div)
Load (1 A/div)
Load (1 A/div)
50.0 ms/div
50.0 ms/div
250-mA Transient Adjustable Converter (Output Set To 12 V)
(VIN = 10 V) VOUT (100 mV/div)
Load Current (100 mA/div)
200 ms/div
Document Number: 70874 S-20642--Rev. B, 13-May-02
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Si9137
Vishay Siliconix
STANDARD APPLICATION CIRCUIT
VIN C7 33 mF CMPD2836 VIN C1 0.1 mF BST3 BST5 DH5 DH3 LX3 Q4 Si4812DY LX5 C3 330 mF DL5 VL D1B C2 0.1 mF Q2 Si4416DY L1, 10 mH R2 0.02 W C4 33 mF +5 V up to 30 mA D1A C5 4.7 mF
Q1 Si4416DY
+5 VOUT
+3.3 VOUT
R1 0.02 W
L2 10 mH
Q3 Si4812DY C6 330 mF
DL3
CS5
FB5 D3 BSTFY DHFY LXFY 20 kW FB3 DLFY RESET PGND* RUN/STOP 0.2 W R3 R5 CSP D2, BYS10-35 CMPD2836 C8 0.1 mF VL C9 4.7 mF Q5 Si2304DS L3, 10 mH
CS3
D4, BYS10-35
VFLYBACK +5 to +12 V C10 100 mF
Q6 Si2304DS
GND*
SEQ
CSN FBFY
+3.3 V up to 1 mA C11 1 mF
REF GND
COMP PGND C12 120 pF R6
*PGND and GND planes should be connected to a single point ground.
where: R5 ) R6 V FLYBACK + R6
V REF
FIGURE 1.
www.vishay.com Document Number: 70874 S-20642--Rev. B, 13-May-02
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Si9137
Vishay Siliconix
TIMING DIAGRAMS
The converter is enabled RUN/STOP VIN is applied VIN
LDO is activated after VIN is applied REF circuit is activated after VL becomes available After VREF goes above 2.4 V, the converter is turned on
VL 2.4 V VREF
OSC EN (Sysmon EN)
Oscillator is activated
OSC 4 ms fmax (SS) High-side gate drive duty ratio gradually increases to maximum tBBM Slow soft-start gradually increases the maximum inductor current
DH
DL
Low-side gate drive
FIGURE 2. Converter is Enabled Before VIN is Applied
The converter is enabled RUN/STOP VIN is applied VIN LDO is activated after VIN is applied VL 2.4 V VREF REF circuit is activated after VL becomes available After VREF goes above 2.4 V, the converter is turned on
OSC EN (Sysmon EN) Oscillator is activated OSC 4 ms Slow soft-start gradually increases the maximum inductor current
fmax (SS)
DH
DL
FIGURE 3. Converter is Enabled After VIN is Applied
Document Number: 70874 S-20642--Rev. B, 13-May-02
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Si9137
Vishay Siliconix
TIMING DIAGRAMS
VIN
[ V (VL)
VL 4V 3.4 V
RESET
VREF
OSC EN (Sysmon EN)
OSC
DH
DL
fmax (SS)
FIGURE 4. Power Off Sequence
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Document Number: 70874 S-20642--Rev. B, 13-May-02
Si9137
Vishay Siliconix
DETAILED FUNCTIONAL BLOCK DIAGRAMS
FB5 + 1X _ CS_ FB_ RX Internal voltage divider is only used on 5-V output.
- REF +
Error Amplifier PWMCMP - + Pulse Skipping Control 20 mV Current Limit DL Logic Control LX_ BBM VL DL SEQ RUN/STOP DH BST_ DH
RY
SLC
V Soft-Start t SYNC Rectifier Control
FIGURE 5. Buck Block Diagram (3.3-V and 5-Controllers)
FBFY
R2
Error Amplifier - REF + - + COMP
SEQ PWM Comparator
RUN/STOP BSTFY
R3
Logic Control
DH LXFY DHFY
C/S Amplifier CSP CSN - + - 100 mV + Current Limit V Soft-Start t Pulse Skipping Control DL DLFY
FIGURE 6. Buck-Boost Block Diagram (5- to 12-V Adjustable Controller)
Document Number: 70874 S-20642--Rev. B, 13-May-02
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Si9137
Vishay Siliconix
DETAILED FUNCTIONAL BLOCK DIAGRAMS
VIN
5-V Linear Regulator FB5 CS5 BST5 DH5 LX5 DL5
VL 4V
5-V Buck Controller 4.5 V
3.3-V Reference 2.4 V
Logic Control 3.3-V Buck Controller
FB3 CS3 BST3 DH3 LX3 DL3
RUN/STOP SEQ 5- to 12-V Adjustable Flyback Controller FBFY CSP CSN BSTFY DHFY LXFY DLFY
RESET
FIGURE 7. Complete Si9137 Block Diagram
DESCRIPTION OF OPERATION
Shutdown Mode The logic threshold for the RUN/STOP pin is 1.6 V. Input voltage must be 0.8 V or less for logic low and 2.4 V or higher for logic high. Start-up Sequence Start-up is controlled by RUN/STOP in conjunction with SEQ. If SEQ is tied to GND, the 5-V SMPS output will come up first, followed by the 3.3-V output and then the adjustable 5- to 12-V output. If SEQ is tied to VL, then the 3.3-V SMPS output will come up first, followed by the 5-V and then the adjustable 5- to 12-V output. When the first SMPS output voltage is within tolerance, the second SMPS will begin its soft-start cycle. When the second SMPS output is within tolerance, the third SMPS will start its soft-start cycle. When both the 3.3-V and 5-V SMPS outputs are within tolerance and 32,000 clock cycles (typically equal to 107 ns) have elapsed since the second SMPS output went into
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regulation, the RESET pin will be pulled high, signifying that all converters are operating correctly ( see RESET Power Good Voltage Monitor). The Si9137 converts a 5.5-V to 30-V input voltage to five different output voltages; two buck (step-down) high current, PWM, switch-mode supplies of 3.3 V and 5 V, one "flyback" PWM switch-mode supply adjustable from 5 V to 12 V, one precision 3.3-V reference and one 5-V between low drop out (LDO) linear regulator output. Switch-mode supply output current capabilities depend on external components (can be selected to exceed 10 A). In the standard application circuit illustrated in Figure 1, each buck converter is capable of delivering 5 A, with the flyback converter delivering 250 mA. The recommended load current for the precision 3.3-V reference output is less than 1 mA, and for the 5-V LDO output is less than 30 mA. In order to maximize power efficiency of the converter, when the 5-V buck converter output (FB5) voltage is above 4.5-V, the internal 5-V LDO is turned off and VL is supplied by the 5-V converter output.
Document Number: 70874 S-20642--Rev. B, 13-May-02
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Si9137
Vishay Siliconix
DESCRIPTION OF OPERATION (CONT'D)
Buck Converter Operation: Current Limit: Buck Converters When the buck converter inductor current is too high, the voltage across pin CS3(5) and pin FB3(5) will exceed approximately 125 mV causing the high-side MOSFET to be turned off instantaneously regardless of the input, or output condition. The Si9137 features clock cycle by clock cycle current limiting capability. Flyback Converter Operation: The Si9137 has an adjustable 5-V to 12-V output non-isolated buck-boost converter, called for brevity a flyback. The input voltage range can span above or below the regulated output voltage. It consists of two n-channel MOSFET switches that are turned on and off in phase, and two diodes. Similar to the buck converter, during the light load conditions, the flyback converter will switch at a frequency lower than the internal clock frequency, which can be defined as pulse skipping mode (PSM); otherwise, it operates in normal PWM mode. The output voltage of the flyback converter is set by two resistors (R5 and R6, see Figure 1) where,
R5 ) R6 R6
The 3.3-V and 5-V buck converters are both current-mode PWM and PSM (during light load operation) regulators using high-side bootstrap n-channel and low-side n-channel MOSFETs. At light load conditions, the converters switch at a lower frequency than the clock frequency. This operating condition is defined as pulse-skipping. The operation of the converter(s) switching at clock frequency is defined as normal operation.
Normal Operation: Buck Converters
In normal operation, the buck converter high-side MOSFET is turned on with a delay (known as break-before-make time tBBM), after the rising edge of the clock. After a certain on time, the high-side MOSFET is turned off and then after a delay (tBBM), the low-side MOSFET is turned on until the next rising edge of the clock, or the inductor current reaches zero. The tBBM (approximately 25 ns to 60 ns), has been optimized to guarantee the efficiency is not adversely affected at the high switching frequency and a specified minimum to account for variations of possible MOSFET gate capacitances.
V FLYBACK +
V REF
During the normal operation, the high-side MOSFET switch on-time is controlled internally to provide excellent line and load regulation over temperature. Both buck converters should have load, line, regulation to within 0.5% tolerance.
Normal Operation: Flyback Converter In normal operation mode, the two MOSFETs are turned on at the rising edge of the clock, and then turned off. The on time is controlled internally to provide excellent load, line, and temperature regulation. The flyback converter has load, line and temperature regulation well within 0.5%. Pulse Skipping: Flyback Converter Under the light load conditions, similar to the buck converter, the flyback converter will enter pulse skipping mode. The MOSFETs will be turned on until the inductor current increases to such a level that the voltage across the pin CSP and pin CSN reaches 410 mV, or the on time reaches the maximum duty cycle. After the MOSFETs are turned off, the inductor current will conduct through two diodes until it reaches zero. At this point, the flyback converter output will rise slightly above the regulation level, and the converter will stay idle for one or several clock cycle(s) until the output falls back slightly below the regulation level. The switching losses are reduced by skipping pulses preserving the efficiency during light load.
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Pulse Skipping: Buck Converters
When the buck converter switching frequency is less than the internal clock frequency, its operation mode is defined as pulse skipping mode. During this mode, the high-side MOSFET is turned on until VCS-VFB reaches 20 mV, or the on time reaches its maximum duty ratio. After the high-side MOSFET is turned off, the low-side MOSFET is turned on after the tBBM delay, which will remain on until the inductor current reaches zero. The output voltage will rise slightly above the regulation voltage after this sequence, causing the controller to stay idle for the next clock cycle, or several clock cycles. When the output voltage falls slightly below the regulation level, the high-side MOSFET will be turned on again at the next clock cycle. With the converter remaining idle during some clock cycles, the switching losses are reduced preserving conversion efficiency during the light output current condition.
Document Number: 70874 S-20642--Rev. B, 13-May-02
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Si9137
Vishay Siliconix
DESCRIPTION OF OPERATION (CONT'D)
Current Limit: Flyback Converter Similar to the buck converter; when the voltage across pin CSP and pin CSN exceeds 410-mV typical, the two MOSFETs will be turned off regardless of the input and output conditions. Grounding: There are two separate grounds on the Si9137, analog signal ground (GND) and power ground (PGND). The purpose of two separate grounds is to prevent the high currents on the power devices (both external and internal) from interfering with the analog signals. The internal components of Si9137 have their grounds tied (internally) together. These two grounds are then tied together (externally) at a single point, to ensure Si9137 noise immunity. This separation of grounds should be maintained in the external circuitry, with the power ground of all power devices being returned directly to the input capacitors, and the small signal ground being returned to the GND pin of Si9137. RESET Power-Good Voltage Monitor The power-good monitor generates a system RESET signal. At first power-up (RUN/STOP going high), RESET is held low until the 3.3-V, 5-V outputs are in regulation and beyond the UVLO timer. At this point, an internal timer begins counting oscillator pulses and RESET continues to be held low until 32,000 cycles have elapsed. After this timeout period, 107 ms @ 300 kHz, RESET is actively pulled up to VL, when the recommended 20-kW resistor to VL is on the RESET pin. Output Overvoltage Protection The 5-V and 3.3-V SMPS outputs are monitored for overvoltage. If either output is typically more than 10% above the nominal regulation point, all low-side gate drivers are latched high until RUN/STOP is toggled. This action turns on the synchronous rectifier MOSFETs with a 100% duty cycle, in turn rapidly discharging the output capacitors and forcing all SMPS outputs to ground. Output Undervoltage Protection Each of the Si9137 5-V and 3.3-V SMPS outputs has an undervoltage protection circuit that is activated 6,144 clock cycles (20.48 ms) after the SMPS is enabled. If either SMPS output is typically under 70% of the nominal value, all SMPSs are latched off and their outputs are clamped to ground by the synchronous rectifier MOSFETs. The SMPS will not restart until RUN/STOP is toggled. Stability: Buck Converters: In order to simplify designs, the 5-V and 3.3-V supplies do not require external frequency compensation. Meanwhile, it achieves excellent regulation and efficiency. The converters are current mode control, with a bandwidth substantially higher than the LC tank dominant pole frequency of the output filter. To ensure stability, the minimum capacitance and maximum ESR values are:
C LOAD w V REF 2p x
V OUT x R CS x BW
ESR v
V OUT x Rcs V REF
where VREF = 3.3 V, VOUT is the output voltage (5 V or 3.3 V), Rcs is the current sensing resistor in ohms and BW = 50 khz With the components specified in the application circuit (L = 10 mH, RCS = 0.02 W, COUT = 330 mF, ESR approximately 0.1 W), the converter should have a bandwidth of approximately 50 kHz, with minimum phase margin of 65_, and dc gain above 50 dB. Other Outputs The Si9137 also provides a 3.3-V reference which can be externally loaded up to 1 mA, as well as, a 5-V LDO output which can be loaded up to 30 mA, or even more depending on the system application. When the 5-V buck converter is turned on, the 5-V LDO output is shorted with the 5-V buck converter output, so its loading capability is substantially increased. For stability, the 3.3-V reference output requires a 1-mF capacitor, and the 5-V LDO output requires a 4.7-mF capacitor.
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Document Number: 70874 S-20642--Rev. B, 13-May-02

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